A phase locked loop (PLL) of the generic type is specified in the printed document U.S. Pat. No. 6,008,703. This document describes a frequency synthesizer in which a ΣΔ PLL is used to produce a signal at a modulated carrier frequency. This phase locked loop, which is shown by way of example in FIG. 2A in the indicated prior art document, comprises a forward path with a phase detector, a loop filter and a controlled oscillator and a feedback path which couples the output of the oscillator to the phase detector via a multimodulus divider. To control the multimodulus divider, a digital sigma-delta modulator is provided whose input side is supplied both with information about the desired carrier signal and with digital modulation data. The modulated output signal is provided at the output of the controlled oscillator.
In a phase locked loop of the generic type, the desired frequency modulation is performed digitally by varying the frequency division value. Such frequency synthesizers are used, by way of example, in modern, digital radio systems for carrier frequency generation and for digital frequency modulation.
When stipulating the dimensions of or designing such a phase locked loop, the choice of bandwidth for the phase locked loop is of particularly great importance. In this context, it is necessary to find a compromise between the noise properties of the circuit and the modulation bandwidth. On the one hand, the noise needs to be as low as possible in order to adhere to the spectral transmission masks prescribed in the various radio specifications. This requires the selection of a relatively small loop bandwidth. On the other hand, this is opposed by the fact that transmitting modulated data requires a large bandwidth for modern applications in communications technology.
By way of example, the European Telecommunications Standard “ETSI EN 300 175-2 V1.5.1 (2001-02) DECT (Digital Enhanced Cordless Telecommunications) CI (Common Interface) PART 2: Physical Layer” specifies limits for unwanted radio emissions. The maximum power level for the third and fourth adjacent channels is limited to 80 nW and 40 nW, respectively, for example, see section 5.5, page 24.
A system-related, dominant noise component arises through the quantization noise of the ΣΔ modulator itself. The ΣΔ modulator normally actuates the multimodulus divider and in so doing brings about random changeover between integer division ratios in order to obtain on average that division ratio which brings about generation of the desired output frequency from the PLL.
FIG. 10A of the prior art document U.S. Pat. No. 6,008,703 (which was cited earlier herein) shows a multimodulus divider which comprises a series circuit containing a plurality of frequency divider stages. In this case, the frequency divider stages can each be changed over between precisely two division values and can divide the input frequency either by the division value 2 or by the division value 3. Such frequency divider stages are also called 2/3 frequency dividers. The range of division values which can be set for such a multimodulus divider, which is constructed only from 2/3 divider stages, is determined in line with the following specification:
  N  =            N      o        +                  ∑                  i          =          0                          L          -          1                    ⁢                        c          i                ·                  2          i                    where L denotes the number of 2/3 divider stages and N0 is equal to 2L.
The ΣΔ modulator actuating such a multimodulus divider is normally implemented in a “MASH” architecture. A stage in such a multistage MASH modulator is shown by way of example in FIG. 8B of the prior art document U.S. Pat. No. 6,008,703. In this case, a summing element is provided which has two inputs and an output, with an error signal being fed back by means of a feedback path. In this arrangement, the error signal is normally fed back with a delay. A multistage ΣΔ modulator with MASH architecture is illustrated in FIG. 8A with the aid of a block diagram.
The ΣΔ modulator distributes the power of the quantization noise in line with its noise transfer function over the frequency band. The noise transfer function (NTF) of the MASH structure can be described by the equationNTZ(z)=(1−z−1)Nwhere N represents the order of the modulator. The quantization noise is in this case shifted from lower frequencies to higher frequencies. The actuation of the multimodulus divider by the ΣΔ modulator brings about random changeover of the division values in line with the spectral distribution of the quantization noise. The random changeover of the division factor in turn brings about a change in the frequency over time and thus produces a “frequency or phase interference swing” (FM or PM interference swing). This is also called residual FM jitter in the literature, or else phase noise. The magnitude of this interference swing determines the signal-to-noise ratio (SNR) of the frequency-modulated or phase-modulated carrier signal and therefore has significant effects on the performance of a radio receiver of such design, for example on its range.
In the case of the frequency synthesizer based on U.S. Pat. No. 6,008,703, the explained noise demands mean that the bandwidth of the phase locked loop is made significantly smaller than is actually required for transmitting the modulated data. To compensate for the resultant frequency response of the loop filter in the PLL, the data to be modulated are subjected to digital precompensation before being supplied to the ΣΔ modulator. This involves high frequency components being raised digitally.
A fundamental drawback of this design is the very accurate matching which is required between the digital compensation filter, on the one hand, and the analog loop filter, on the other. This is because if the bandwidth of the control loop changes as a result of analog influences such as manufacturing tolerances, temperature drifts or ageing phenomena, the digital precompensation (which is not subject to these influences in practice) raises the high frequency components too much or too little.
Another option for compensating for a reduced loop bandwidth is provided by “two-point modulation”. This involves modulation at two modulation points in the phase locked loop, first on the frequency divider and secondly at the oscillator input. In this case, one of the two modulation points of the PLL has low-pass filter properties and the other has high-pass filter properties. The overall result is therefore a constant transfer function for the modulation data. In this case too, however, the problem of accurate matching being required between the analog and digital signal paths (which problem has already been explained) arises.